Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI strongly recommend you look through the following document: external memory interface handbook volume 5 - section i. altmemphy design tutorials (http://www.altera.co.uk/literature/hb/external-memory/emi_tut_ddr.pdf).
This discusses in great depth connecting DDR memory to FPGAs. Yes, there are dedicated pins for the data. Pin selection for the control bus (address, cs, wr etc.) is a little more flexible. I recommend you put a design together and let the tools give you a pinout. You can either use this as is or make changes, each time confirming, with Quartus, that the pin changes you're making can be supported. Regards, Alex