Cyclone II + NIOS design crashes with high IO pin drive strength

The JTAG signal routing looks reasonable. Yes, it is a TQFP package.

Each VCCIO pin has its own adjacent 0.1uF capacitor on the same PCB side as the FPGA.

The clock to the SDRAM from the FPGA has a 68R series terminating resistor adjacent to the FPGA, then the track goes off to the SDRAM.

(The data tracks are 8mil (0.208mm), so I calculate the microstrip track impedance to be 87R)

The 3.3V is well decoupled on the board by a 1000uF electrolytic, numerous 10uF tantalums and innumerable (0603) 0.1uF ceramic caps.

However, the 3.3V regulator is not on the PCB; the 3.3V it is supplied from an external SMPS, and it enters the board via a MURATA - BNX002-01 - DC FILTER.

Ref: http://search.murata.co.jp/ceramy/image/img/pdf/eng/l0117bnx00.pdf

As you can see from this datasheet this filter goes between the PCBs the ground-plane and the 3.3V plane, and the external SMPS's 3.3V and ground.

I don't know if this is relevant to the problem or not?

Could this PSU arrangement and/or the input filter be contributing to ground bounce, transient voltage sag, or some other electrical ailment?

NB: I didn't do the PCB design I am just debugging it for a client.