Cyclone II + NIOS design crashes with high IO pin drive strength

Higher I/O strength = fast edge transitions = more coupling to other traces and higher current requirements from the power supply.

It sounds like you have a layout issue on your new board, eg., traces routed too close to each other, or a clock missing a termination resistor.

If the problem occurs with the JTAG interface, take a look at those signals with a scope. Perhaps there is a clock-like signal routed nearby that is coupling onto the JTAG signals.

If the FPGA package is a TQFP, do the VCC pins have decoupling capacitors on the same side of the PCB as the FPGA, i.e., right next to the power pins?

Cheers,

Dave