--- Quote Start ---
The 100MHz clock comes from a frequency synthesiser (X4) and is driven into the FPGA via a clock buffer (U25, an IDT ICS8543).
The first (CLKA_IN_x0) drives a differential clock into dedicated clock inputs in bank 8B (pins L11 & K11).
The second (CLKA_IN_x1) a differential clock into dedicated clock inputs in bank 3B (pins V11 & W11).
The frequency synthesiser is controlled from the MAX II controller. It defaults to 100MHz but you can set the frequency of it through Altera's 'Clock Control' application. You can use the app to reset the frequency back to 100MHz.
Note: the clock buffer has two clock inputs; X4 and the LVPECL SMA connectors on the board. To ensure the resulting clocks come from the frequency synthesiser ensure SW1 'CLK_SEL' is set correctly (ON = 0).
--- Quote End ---
ok, thanks a lot .
Honored Contributor
