Cyclone 3 DDR2 controller - capture clock FIFO

Thanks Jake,

Ok, so I issue a RD command, pipe it a fix number of clock cycles (based in 1: the DDR2 CAS Latency, 2: the number of cycles that takes to cross the asynchronous FIFO and 3: tAC, tco and a few other delays). Let's say it's 6 system clock cycles, at that point I set "RD_VLD" and mark the data popped from the FIFO as valid. In parallel with this the calibration logic is adjusting the phase of the capture clock, once calibration is done we should ideally have:

- a fixed phase offset between the capture clock and the system clock

- a fixed pipeline length for the RD_VLD signal

uhmm, 2 questions here:

a) the number of system clock cycles that takes for a data to cross the asynchronous FIFO, is it fixed?

b) do we need to change the RD_VLD pipe length as part of the calibration process? SLOW and FAST corner models vary a lot in timing, maybe more than a whole DDR2 clock, so I was wondering if a FAST silicon could actually sample the data one clock earlier than an SLOW silicon, i.e. the calculation of 5 system clocks for RD_VLD could be for a FAST corner models and maybe 6 for a SLOW corner model. So the calibration should run a 1st phase shifting cycle with a pipe of 5 and a 2nd (if needed) with a pipe of 6...

Regards,

-Ulises