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Altera_Forum
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16 years ago

Cyclone 3 DDR2 controller - capture clock FIFO

Hello, I'm using the Cyclone III 3C120 eval.board to evaluate a design for a customer. I am planning to use my own DDR2 controller using a capture clock, in a similar way to what it's explained...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Keep in mind that there is only a phase difference between your system clock and capture clock. You should continually pass data through the FIFO ("push" and "pop" on every clock). You just need to know (in the system clock domain), the latency between when you expect the read data and when it actually arrives (the output of your FIFO). You discard any samples between valid samples.

So yes, pipeline your RD command (or an expect command from your controller). Then you just need to do the work to find out when valid data arrives back in the system clock domain. By the way, that latency may change depending on frequency.

Coincidentally, I've never used the FIFO approach. I've always used a 3rd clock (resync clock) between the capture and system clock domains. But the FIFO would actually likely be easier.

Jake