Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThen I must question whether the .sof you are using to generate the .jic is the same file as you are using when programming directly.
Assuming it is - are you happy that you are testing the device in the same way when programming in each way? Is there logic in the device to gate the clock under certain conditions? Is it being gated when programmed from EPCS and not when programmed directly - i.e. is this happening by design? Regards, Alex