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Honored ContributorCyclone 2 + MLVDS transciever = PLL problem?
Hi
We are using a NIOS2 processor and some VHDL code inside a Cyclone 2 240 pin package. Connected to the FPGA are 2 SRAM chips, EPCS16 and a couple of MLVDS transceivers, namely MLVD080 and MLVD205 from TI. This is the problem we are experiencing on our boards: If the system is configured to run directly from the input clock 32.768MHz on pin 92 then the system runs fine (NIOS and VHDL). But if we use the PLL with the VDDD and VDDA on pins 121 and 123 respectively the PLL loses lock with the frequency of the accesses to the MLVD080. The power supply for the PLL is as recommended by Altera (VDDA is filtered with a ferrite bead and a bank of capacitors from 2u2 down to 10nF, same for VDDD without the ferrite bead). The MLVD is blocked on its power supply with 100nF capacitors, also we tried adding bigger capacitors, 22uF, with no result. VDDD was also filtered the same way as VDDA, no effect. The board has 4 layers, with a power plane covering the whole board with cutouts for the 1.2V supply rail and a ground plane. Surrounding the PLL are data lines that go to and from the MLVD. We are contempt with the design running without the PLL but we would like to know what is behind this problem, since it may arise in the future the need for the PLL. Thank you in advance. :)11 Replies
Altera_ForumMy experience is, that PLL loose of lock with Cyclone II is mainly related to simultaneous switching outputs (SSO) generated ground bounce. I had a case, where it was impossible to operate a 32 bit data bus in a PQFP240 Cyclone II device, the issue was solved by configuring the bus to 16 bit, which was possible there, fortunately.
In the reported case, also the board layout and supply decoupling had been state of the art, actually no switching noise could be measured at the supply pins. From the circuit behaviour, it was obvious, that switching bus outputs caused loose of lock, but we couldn't reveal for sure, if the final reason was in ground bounce disturbing the clock input or the PLL analog supply. As we found a workaround, there was no high pressure to find a final solution. Although it wasn't verified, if single ended input clock contributes to the problem, I used a differential (LVDS) clock supply in several later design, hoping that it would be almost immune to ground bounce. New designs are also using Cyclone III, which is apparently less sensitive to analog supply interference for it's internal PLL voltage regulator. It also turned out, that PQFP240 is more susceptible to ground bounce than other packages due to large lead frame and long bond wires. Altera hasn't defined simultaneous switching output limits for single ended IO as e. g. for voltage referenced standards, but interferences may occur anyway, particularly with large PQFP package.
