Cyclone 2 + MLVDS transciever = PLL problem?

My experience is, that PLL loose of lock with Cyclone II is mainly related to simultaneous switching outputs (SSO) generated ground bounce. I had a case, where it was impossible to operate a 32 bit data bus in a PQFP240 Cyclone II device, the issue was solved by configuring the bus to 16 bit, which was possible there, fortunately.

In the reported case, also the board layout and supply decoupling had been state of the art, actually no switching noise could be measured at the supply pins. From the circuit behaviour, it was obvious, that switching bus outputs caused loose of lock, but we couldn't reveal for sure, if the final reason was in ground bounce disturbing the clock input or the PLL analog supply. As we found a workaround, there was no high pressure to find a final solution.

Although it wasn't verified, if single ended input clock contributes to the problem, I used a differential (LVDS) clock supply in several later design, hoping that it would be almost immune to ground bounce. New designs are also using Cyclone III, which is apparently less sensitive to analog supply interference for it's internal PLL voltage regulator.

It also turned out, that PQFP240 is more susceptible to ground bounce than other packages due to large lead frame and long bond wires. Altera hasn't defined simultaneous switching output limits for single ended IO as e. g. for voltage referenced standards, but interferences may occur anyway, particularly with large PQFP package.