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Altera_Forum
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17 years ago

Cyclone 2 + MLVDS transciever = PLL problem?

Hi We are using a NIOS2 processor and some VHDL code inside a Cyclone 2 240 pin package. Connected to the FPGA are 2 SRAM chips, EPCS16 and a couple of MLVDS transceivers, namely MLVD080 and MLVD...
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Altera_Forum
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17 years ago

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Hi Milosd..

Sorry for the confusion.. :(

My question is, is pin 92 on your cyclone II the same point as the clock pins on your sram? If you can send me a diagram, or a brief schematic of your system, that will be very helpfull..

Thanks you very much for replying

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Hmm I think you have a different RAM in mind... We are using Static RAM, meaning he doesn't require any clocks for operation since everything is tied to enable pins (write, read...) See the schematic attached.