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Hi Miilsod
Thanks for the reply..
I just have a couple of followup questions, because i am having the same issue with the SSRAM.
1) what clock is feading your ram...is it direct from your crystal, or does it go through the first?
2) can you elaborate further on the statement "just take care when connecting pins for byte enable and current limits if they are close and no resistors present on the lines
http://www.alteraforum.com/images/smilies/smile.gif "
Thanks
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1. how can u feed clock through the ram first? :P You must mean the PLL? No, the clock feeds the design directly, inside the design the clock enters NIOS cpu and inside the cpu the design is as follows:
- cpu
- jtag uart
- tri_state_bridge
- sram
and some other components.
The same clock is used to drive peripheral VHDL logic in the same FPGA.
2. well you have to connect the correct BE to the address lines if you're using two SRAM chips otherwise strange things may happen (search for forum on NIOS printf problems, there are a couple of threads on that subject). As for current limits we found out that we had a bit of overshot or ground bounce, it manifested diferently on two identical boards, the solution was to limit drive current on sram pins.
I hope i was clear enough, but you're still welcome with questions ;)
Honored Contributor
