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Altera_Forum
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18 years ago

Cyclone 2 + MLVDS transciever = PLL problem?

Hi We are using a NIOS2 processor and some VHDL code inside a Cyclone 2 240 pin package. Connected to the FPGA are 2 SRAM chips, EPCS16 and a couple of MLVDS transceivers, namely MLVD080 and MLVD...
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Altera_Forum
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18 years ago

Hi Miilsod

Thanks for the reply..

I just have a couple of followup questions, because i am having the same issue with the SSRAM.

1) what clock is feading your ram...is it direct from your crystal, or does it go through the first?

2) can you elaborate further on the statement "just take care when connecting pins for byte enable and current limits if they are close and no resistors present on the lines http://www.alteraforum.com/images/smilies/smile.gif "

Thanks http://www.alteraforum.com/images/smilies/smile.gif