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Altera_Forum
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18 years ago

Cyclone 2 + MLVDS transciever = PLL problem?

Hi We are using a NIOS2 processor and some VHDL code inside a Cyclone 2 240 pin package. Connected to the FPGA are 2 SRAM chips, EPCS16 and a couple of MLVDS transceivers, namely MLVD080 and MLVD...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi

"If the system is configured to run directly from the input clock 32.768MHz on pin 92 then the system runs fine (NIOS and VHDL)". how did you get the phase shift between the nios processor and the sram if u use the input clock?

Thanks