Cyclone 10LP and Cyclone 10GX - Are they really new?

Hi,

1. Process of cyclone III and Cyclone 10 LP there is conflict in the documents below for cyclone III one documents tell it is 60nm and other it is 65nm process?

The statement for the Cyclone III build with 60nm is still true. I guess the catalog just lump the 65nm together under as 60nm category. You can check the information from the each FPGA device Configuration handbook chapter.

Cyclone 10 LP devices are manufactured using the TSMC 60-nm low-k dielectric process.

Cyclone IV devices are manufactured using the TSMC 60-nm low-k dielectric process.

Cyclone III devices are manufactured using the TSMC 65-nm low-k dielectric process.

Cyclone III LS devices are manufactured using the TSMC 60-nm low-k dielectric process.

2. how 50% power reduction of Cyclone 10 LP is claimed compared to the 28nm Cyclone V?

I believe the statement here focus on the lower power static being offer in Cyclone 10 LP. We have reduced the power of Cyclone 10 LP, compared to previous generations of Cyclone, by tuning the fab process to be more aggressive for meeting lower static power. The benchmark comparison among Cyclone family device was done which in result for among the non-transceiver Cyclone series devices, Cyclone 10 LP leads with the lowest cost and power.

3.Is there Cyclone 10 SoC in pipeline?

There are no plans for an SoC variant.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)