Forum Discussion
GLees
Contributor
ContributorCyclone 10GX LVDS SERDES & DPA
I am starting a design using the Cyclone 10GX LVDS SERDES IP with DPA. I would like to verify that if I instantiate a 4-channel design, the SERDES IP will do DPA independently on each channel. This m...
AqidAyman_Altera
Regular Contributor
Regular ContributorBased on the user guide, you can configure each LVDS SERDES IP core channel as a receiver for a single differential I/O.
Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.
