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EDing's avatar
EDing
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7 years ago

Cyclone 10, Passive Serial configuration Issues

We are using a Microcontroller to do this. We tested the programming software of the MCU on a Cyclone IV FPGA. I’m finding this was very much easier to do. There are different MSEL schemes for Pass...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
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7 years ago

Hi Eding,

Can you provide your schematic for me to check the dedicated configuration pin connection? You don't need to provide the full schematic, you can just provide the schematic that contains the dedicated configuration pin connection.

Regards,

Nooraini

  • EDing's avatar
    EDing
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    7 years ago

    Schematic images attached for FPGA Passive Serial

    • EDing's avatar
      EDing
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      7 years ago

      ​Hi Nooraini,

      Have you got a chance to check the schematic? Here are more information:

      The Voltage Level translators are from TI. TXS0104 and TXB0104. The TXB0104 is used only on DCLK and DATA0, because is higher speed.

      TXB0104 is used for nSTATUS nCONFIG CFG_DONE and INIT_DONE

      The inputs that are no connects, that we are questioning are:

      CLKUSR is a no connect, will any of the high speed interfaces work if we do not provide a clock to CLKUSR?

      nIO_PULLUP, DEV_CLR, and DEV_OE are also no-connects, hope they are not critical.

      Thanks!