cyclone 10 LP true LVDS transmitter IO banks

HI there,

I am considering to use Cyclone 10 LP for LVDS communication. I am confused the information of official document for explaining the true LVDS transmitter at IO banks.

Although figure 73 description says the location indicates "Top and Bottom", both sides, the description about Figure 72, there is no mention about on the 'LEFT' side but only on "RIGHT" side banks. Does it mean that LEFT banks does not have true LVDS output buffer?

On below page,

https://www.intel.com/content/www/us/en/docs/programmable/683777/current/lvds-i-o-standard-in-devices.html

"The Intel® Cyclone® 10 LP left and right I/O banks (row I/Os) support true LVDS transmitters. The top and bottom I/O banks support emulated LVDS transmitters with external resistors.

For the LVDS receiver, you require an external 100 Ω termination resistor between the two signals at the input buffer.