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BCrowell's avatar
BCrowell
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2 years ago

Cyclone 10 LP Remote Update Simulation

I am trying to figure out the details on the remote update so I downloaded the example project (Cyclone 10 LP Remote System Upgrade Design Example) and set up a simulation to run rather than just use it on the eval board. However, the remote update core doesn't seem to respond to any of the reads I added with correct data. The relevant data bits are always X's for the reads I did, one to the trigger register and one to the config address register. See the attached screen grab for the waveforms. I am wondering if there is an issue with the simulation model of the core or is there something different that needs to be done to properly read the data from the core?

Thanks

Brad

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  • BCrowell's avatar
    BCrowell
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    2 years ago

    Aiman,

    I'm not sure which document you are referring to. I don't see anything attached to your message...

    Brad

  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
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    2 years ago

    Hi,


    Thanks for the update.

    Quick check, did you follow the document below when using Questa?


    Regards,

    Aiman


  • BCrowell's avatar
    BCrowell
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    2 years ago

    No I am running a function simulation in Questa. I'm not using it on a board as I assume this will work just fine. What I am trying to do is gain some insight into the process by simulating it in Questa so I can see the details, rather than just that the board reconfigures as indicated by the LEDs.

    Thanks

    Brad

  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,


    Thank you for contacting Intel community.


    By setting up simulation, does it mean you run the design using your own board?


    Can you run the design using evaluation board by following the userguide? And see if it works fine?


    Regards,

    Aiman


  • BCrowell's avatar
    BCrowell
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    2 years ago

    Digging through the code I have traced the source of the X's in the data to the cyclone10lp_rublock instantiated as sd4 within the altera_remote_update_core.v file. The regout port of this block connected to signal wire_sd4_regout is always hiZ, which I believe is causing the read data to eventually become X. The cyclone10lp_rublock seems to be a black box as far as I can see so I can't trace this back any further.