Cyclone 10 LP DDR IO-cell information

I re-compiled my test program for both Cyclone 10 LP and Cyclone IV E.

-- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity scgige is
    port(
        Clk      : in    std_logic;
        DdrIn    : in    std_logic_vector(0 downto 0);
        SdrOut   : out   std_logic_vector(1 downto 0);
        DdrIO    : inout std_logic_vector(0 downto 0);
        SdrIOOut : out   std_logic_vector(1 downto 0);
        SdrIOIn : in    std_logic_vector(1 downto 0);
        DdrIOdir : in    std_logic
    );
end entity scgige;
architecture RTL of scgige is
    signal lsdrh : std_logic_vector(0 downto 0);
    signal lsdrl : std_logic_vector(0 downto 0);
    signal tddriodatainh : std_logic_vector(1-1 downto 0);
    signal tddriodatainl : std_logic_vector(1-1 downto 0);
    signal tddrio_DataOutH : std_logic_vector(1-1 downto 0);
    signal tddrio_DataOutL : std_logic_vector(1-1 downto 0);
begin
    tddrin : altddio_in
        generic map(
            width => 1
        )
        port map(
            aclr      => '0',
            aset      => '0',
            datain    => DdrIn,
            dataout_h => lsdrh,
            dataout_l => lsdrl,
            inclock   => Clk,
            inclocken => '1',
            sclr      => '0',
            sset      => '0'
        );
    process(Clk) is
    begin
        if rising_edge(Clk) then
            SdrOut <= (lsdrh(0) & lsdrl(0));
            SdrIOOut <= (tddrio_DataOutH(0) & tddrio_DataOutL(0));
            tddriodatainh(0) <= SdrIOIn(1);
            tddriodatainl(0) <= SdrIOIn(0);
        end if;
    end process;
    tddrio : altddio_bidir
        generic map(
            width                    => 1
        )
        port map(
            aclr            => '0',
            aset            => '0',
            combout         => open,
            datain_h        => tddriodatainh,
            datain_l        => tddriodatainl,
            dataout_h       => tddrio_DataOutH,
            dataout_l       => tddrio_DataOutL,
            dqsundelayedout => open,
            inclock         => Clk,
            inclocken       => '1',
            oe              => DdrIOdir,
            oe_out          => open,
            outclock        => Clk,
            outclocken      => '1',
            padio           => DdrIO,
            sclr            => '0',
            sset            => '0'
        );
end architecture RTL;