Cyclone 10 GX device issue

Hello Richard,

Sorry to post my delayed response here now.

Yes, I was preparing my simple project these days. I just wanted to think how to create one simple project to explain what I am just asking.

The attached archived project is this created project, please help check it. Which was created based on our current ADC processing project. Please ignore other parts. My question only focuses on 3 nodes or LE cells, which are coded as following

LaunchCT <= operation_mode_sel_sig;
Ch0Hit <= trig(0) when LaunchCT='1' else calibHit;
Ch1Hit <= trig(1) when LaunchCT='1' else calibHit;
Ch2Hit <= start when LaunchCT='1' else calibHit;

u0_carry: carryin_test port map (carryin => Ch0Hit,carryout => cout0);
u1_carry: carryin_test port map (carryin => Ch1Hit,carryout => cout1);
u2_carry: carryin_test port map (carryin => Ch2Hit,carryout => cout2);

There are 3 I/O pins come from outside and they are fed into same logic module which is named as "carryin_test". Which is implemented as following image, so only two ALUTs are used to realize this module.

I have added physical location constrains for these 3 carryin cells and make them closed to those 3 I/O pins.

Above image shows the constrain format, however, only the third can be applied. The first two constains will push Quartus giving errors imformation:

Could you give me the expalnation about above error?

I resolved above error to constrain the first two cells as the third cell. It just corrects "N24" to N0. After that, I still get the following warning:

Could you give me the explanation about above waring info? What's the mean of "will be dropped"?

All above comments are just about this simple project creatation. Now let's go back into my primary question about the inside connections of the cell/node. The following image shows the inside of the cell (ALUT). This is very simple, there is only one input signal is fed into this ALUT. It is connected to DATAC of the ALUT. My question is, if ECO is not allowed to use for Cyclone 10GX, is there any other ways to control the input signal to connect to the ALUT input ports? You know I have total 3 I/O input signals, I want to control them to connect the same ALUT input ports, for examle, all connct to DATAC, instead of one connects DATAA, one connects DATAB, and the last one connects DATAC. Which are uncertainty connection. What i need is fixed connection, then i can get almost same time delay for these paths.