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yong's avatar
yong
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3 years ago

Cyclone 10 GX Development Kit JTAG chain error

Hello, I am working on a Cyclone 10 GX Development Kit testing AS Configuration. I use Quartus Programmer tool to program .jic file to QSPI Configuration Device through USB Blaster II cable. It w...
yong's avatar
yong
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thanks Farabi for your response!

I tried another USB Blaster II cable, same issue.

Is the JTAG 10pin connector at the top left of the Development board? If I use oscilloscope to capture signals, should I probe the JTAG 10pin connector? I thought the connector is used for connecting external JTAG debugger.

What do you mean "tap the TCK, TDI and TDO signal at JTAG 10pin connector"? How can I do that?

Thanks!

Yong

yong's avatar
yong
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello Farabi,

Please see below picture of the Cyclone 10 GX Development Kit. The 10 pins JTAG header and Micro USB connector are highlighted in the red circles. I connected USB Blaster II cable to the Micro USB port. According to Cyclone 10 GX Development Kit User Guide, it says 10pin header is optional JTAG for external download cables. Can I probe the 10pin connector to debug JTAG chain issue while using USB Blaster II cable connected to Micro USB port?

Here is part of the Cyclone 10 GX Development Kit diagram.

There are two Max10 FPGA devices on the board. One is for On-board Intel FPGA Download Cable II and Power Management, the other is for PFL configuration, clock generator control and power monitoring. I have a few questions as below:

1. Only one Max10 is detected on the JTAG chain. How can I know which one is on the JTAG chain?

2. Is Max10 have to be configured successfully in order to detect both devices (Max10 and Cyclone10GX) on the JTAG chain? If yes, why I was able to see Cyclone10GX on JTAG chain occasionally while Max10 is not loaded?

3. I manually programmed max10.sof to Max10 and saw it is configured successfully (Quartus message says it is configured successfully). Then get_device_names, most of time it still only shows Max10, no Cyclone10GX.

Thanks!

Yong

  • yong's avatar
    yong
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello Farabi,

    Can you please kindly give me some advices and answers to my questions in my earlier posts? My project has been blocked by this JTAG issue for a few weeks.

    I did further research, here is the JTAG topology of the Cyclone 10 GX development kit.

    Do I have to configure System Intel Max10 in order to see Cyclone 10 GX on the JTAG chain?

    I saw in another post that Intel engineer commented that "If the DIP switch S5.2 is set correctly then you should always observed the Cyclone 10 in the JTAG chain". S5.2 is the switch to enable JTAG chain for Cyclone 10 FPGA. I do have S5.2 set correctly.

    Any other advices are appreciated.

    Please let me know if you need more information from me.

    Thanks!

    Yong

    • yong's avatar
      yong
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hello Intel Tech Support team,

      Can anyone help on this case? This is an urgent issue blocking my project for a few weeks already.

      Any advices are appreciated.

      Thanks!

      Yong