Cyclone 10 GX DDR interface timing / constraint issue

@KTan9: I looked at the phylite IP but am not sure how this would be implemented. I have an ADC interface that provides a 338 clock and four 8-bit wide data inputs that are running at DDR. The phylite IP seems to require a clock input (used as the PLL ref_clk) that is synchronous to the strobe_in input at half the frequency of the interface clock. Would my data inputs DI, DID, and DQ, DQD map to the io_data_in ports and my 338 clock map to the io_strobe_in port? If so where am I supposed to get the ref_clk from that is supposed to be synchronous to strobe_in but half the frequency? Any pointers to what I am missing or not understanding are greatly appreciated!

@sstrell: I have watched the online training and have changed the following things:

• changed PLL mode from LVDS to source synchronous
• added a 90 degree phase shift of the 338 PLL output (in order to align the clock at the center of where the incoming data changes)
• removed the set_multicycle_path constraints

With those changes I am getting timing violations that are worse than before (see updated timing report attached). Also the setup relationship from the DDIO output to the first regular capture register is still showing as half a clock cycle but shouldn't it be a full clock cycle?

I am not sure at this point on how to proceed, is the phylite the right path or can I get the interface timing to pass with the DDIO implementation?

Thank you for your help!