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sidsinha89's avatar
sidsinha89
Icon for New Contributor rankNew Contributor
4 years ago

Cyclone 10 GX (10CX085F672) Device Clock input

Hello All, I am starting to work with Intel FPGAs. I am currently preparing specifications for the new FPGA project. A part of it is to define pin assignment for the module. In my design, I wish ...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


It depends upon the I/O standard assigned to the pin. Bank 2A is a LVDS I/O bank, which supports single-ended I/O standards upto 1.8V.

Refer Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook.

Section 5.4.3, I/O Banks Groups in Intel Cyclone 10 GX Devices,

https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#rfl1487755214207

and

section 5.1.1, I/O and Differential I/O Buffers in Intel Cyclone 10 GX Devices, https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#sam1403481935742


Also refer the device pin-out table for more pin information.


Regards.


sidsinha89's avatar
sidsinha89
Icon for New Contributor rankNew Contributor
4 years ago

Hello!

Thanks for the reply. I shall apologize for not clearly mentioning the relevant details.

All I/Os on FPGA are LVCMOS standard. No Differential I/Os. All banks (2J, 2K, 2L, 2A, 3A) shall be on 1.8V VCCIO.

Under these circumstances, am I right to conclude that I shall be able to use complimentary pins, for instance clk_2a_1n, as normal LVCMOS I/O while clk_2a_1p is used as clock input and connected to ALKCLKCTRL IP block?