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From my brief reading of
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cvp.pdf You can use either. Active serial is used when you want the FPGA to drive the clock to the serial device directly. (The FPGA is directly connected to a serial flash device and the FPGA will just program itself, with no external device required.
In Pasive Serial mode, someone outside the FPGA is driving the clock/data pins. So here a external CPU or CPLD is typically controlling the programming sequence.
For PCIe CvP, from what I can tell, you must still first program at least a basic configuration image via one of the other configuration schemes then your device can be seen on the PCIe bus for the rest of the configuration process.
So to answer your question. If you have a CPU on the same board that has the flash space available, passive serial is an ok method. Otherwise Active serial is the smallest solution.
Pete
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Hi Pete,
Thanks for your reply.
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