CYCLON V + DDR3 RAM reset/clock problems within BeMicro CV board

Start with my DDR3 example ...

http://www.alteraforum.com/forum/showthread.php?t=43992

The reset on the Hard IP core does not work correctly

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Service Request#11062538

Cyclone V DDR3 UniPHY HMC Avalon-MM wait-request lockup after soft-reset

The uploaded zip file contains an example design for the BeMicro-CV device. While testing the DDR3 UniPHY controller, it was determined that pulsing soft-reset caused the Avalon-MM interface to lock-up. A Modelsim simulation was created that reproduces the problem, i.e., for some reason the DDR controller forces wait-request to be asserted after the soft-reset signal has been pulsed. The simulation shows that if the global-reset signal is pulsed, the testbench works fine.

Altera's Knowledgebase article

http://www.altera.com/support/kdb/solutions/rd05212013_358.html

has the comments that

"Altera strongly recommends using only soft_reset_n at all times.

Use global_reset_n only for Power on reset."

So, what is wrong with the Cyclone V Hard-memory controller?

The file altera_service_request.txt has details on how to synthesize and simulate the design example.

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This has yet to be resolved, but the example I have referred you to works fine.

Cheers,

Dave