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yeah dave it's fpga to fpga, were using an LVDS rx input, could that be causing problems? we had to do the pin assignment workaround (setting it to 1.5PCML) (we're using quartus 11.1),external termination, all voltages are fine.
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Could you please clarify.
Are you using an LVDS receiver channel or a transceiver channel?
I don't recall if the common-mode settings on a Cyclone support LVDS levels on the CML inputs. Can you can run a quick test where you AC-couple the signals?
For example, in my tests the signals are on SMA cables, so its easy to put a DC-block on the cables. Perhaps you can do the same.
Cheers,
Dave
Honored Contributor
