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the assumption I have risen today is that sending a constant data packet to the CDR will cause it to derive a clock rate that is half of the actual rate, I am planning on changing our test code to send a switching pattern between 55h and AAh, is my assumption correct?
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Sending 55h continuously should be fine. I'm testing 5Gbps Stratix IV GX links with a 32-bit 00FF00FFh pattern so that I can look at it on a 1GHz scope (312.5MHz).
The CDR PLLs are like high-Q filters. They lock fine to lower rate data streams where the stream has a repeating pattern that is a fraction of the data rate.
Have you tried simulating your link in Modelsim? The ALTGX blocks simulate fine - including responding correctly to the reset sequence.
I would recommend getting a simulation working first, and then when that works, review your hardware setup.
Cheers,
Dave
Honored Contributor
