CYCLON IV GX - ALTGX Won't recieve any valid data

Hey everyone, I'm ggg456's partner for this project, let me clearify and add to what he said:

-Yes, we have checked the physical layer of our boards, all signals look great up to the receiver side of the FPGA.

-we are running the system at 600Mbps in order to view the signal on a scope (in order to check the signal is still properly going in.)

-the assumption I have risen today is that sending a constant data packet to the CDR will cause it to derive a clock rate that is half of the actual rate, I am planning on changing our test code to send a switching pattern between 55h and AAh, is my assumption correct?