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MAlek2's avatar
MAlek2
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7 years ago

Custom PCIe DMA on Cyclone 10GX FPGA burst read stucks

I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM s...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago
Hie, I will need to know the IP configuration used to answer your questions. Hence could you help provide the following. i. Quartus version ii. Device iii. Which QSYS or Paltform IP type used iv. Details on IP configuration. Will it be possible to provide a simplified achieve ".qar" (only containing Quartus IP configuration) without any of your code. Regards, Nathan
  • MAlek2's avatar
    MAlek2
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    7 years ago

    Thank you for your reply, but i've already found out what was wrong. I needed to enable bus mastering to my PCIE device. Without that the host system doesn't allow DMA transactions to end point.