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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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Custom IP from a verilog code

Hi, I could make a custom IP from a verilog module counter.v (attached with this message). It have clock, reset, avalon_ready as input ports and data and avalon_valid as output ports. This is desig...
  • sstrell's avatar
    sstrell
    3 years ago

    The component editor mis-identified your component as an agent instead of a streaming source, so that's why the errors appeared. You fixed the errors by defining the interfaces and signal roles so you are good to go. To avoid this from happening in the future, in your code use the 3-part naming scheme for interface signals discussed in the Platform Designer user guide: <interface type>_<interface name>_<defined signal role>. This automates how Component Editor identifies the signals in your design.

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey


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