Sijith
Occasional Contributor
Occasional ContributorCustom IP from a verilog code
Hi, I could make a custom IP from a verilog module counter.v (attached with this message). It have clock, reset, avalon_ready as input ports and data and avalon_valid as output ports. This is desig...
The component editor mis-identified your component as an agent instead of a streaming source, so that's why the errors appeared. You fixed the errors by defining the interfaces and signal roles so you are good to go. To avoid this from happening in the future, in your code use the 3-part naming scheme for interface signals discussed in the Platform Designer user guide: <interface type>_<interface name>_<defined signal role>. This automates how Component Editor identifies the signals in your design.
