Honored Contributor
Honored ContributorDash25,
You can not make custom instructions with 3 inputs like you descibe it for a MAC. What you need to do is to work with 2 custom instructions. One will access the accumulator register, the other will add the multiple of the two operands and add it to the result. Best performance you will have if you register the multiply output before adding. I'm not good in VHDL (because I never use it), but in verilog it should look as follow :module custom(
input a,
input b,
output reg result, //unclocked
input n,
input start,
input clk, clk_e, reset,
output reg done //unclocked
);
parameter ACC = 0;
parameter MULT = 1;
reg accum;
reg mult;
reg l_start;
always @(posedge clk or posedge reset)
if (reset)
begin
accum <= 0;
l_start <= 0;
end
else
begin
l_start <= start;
if (start)
case (n):
ACC : accum <= 0;
MULT : mult <= a*b;
//possible to add others
endcase
if (l_start)
case (n):
//ACC : nothing to do
MULT : accum = accum + mult;
endcase
end
//the result output
always @*
case (n)
ACC : result = accum;
//MULT : not interesting
default : result = 0;
endcase
//control done behaviour
always @*
case (n)
//ACC : handled with default case;
MULT : done = l_start; //delay one cycle, because calculation still busy
default : done = 1;
endcase
endmoduleinline unsigned long GetAndResetMAC()
{
unsigned long retval;
__asm__ ("custom 0, %0, r0, r0" : "=r" (retval));
return retval;
}
inline void MAC(unsigned short a, unsigned short b)
{
__asm__ ("custom 1, r0, %1, %2", :: "r" (a), "r" (b));
}
