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5 Replies
- Altera_Forum
Honored Contributor
no one to answer to my question?
please help me - Altera_Forum
Honored Contributor
Not sure what your problem is.
IIRC the 'clk_en' signal is basically an indication that the specific custom instruction is being executed. There may be a requirement that some of the output signals not be asserted unless clk_en is asserted - in order to avoid messing up other custom instructions. What you do with any other signals is only constrained by your imagination (and the time available to execute the instruction). - Altera_Forum
Honored Contributor
Your custom instruction should be written to ignore dataa, datab, and n when clock enable is low.
- Altera_Forum
Honored Contributor
--- Quote Start --- Your custom instruction should be written to ignore dataa, datab, and n when clock enable is low. --- Quote End --- In this situation the custom instruction could transmit his entry ("conduit signal" from the another processor ) to his "result" port? Thanks - Altera_Forum
Honored Contributor
Anything on the 'result' port is (or at least should be!) ignored except during the final clock cycle of the instruction.
There is nothing to stop you latching the data and using it when the instruction is being executed - but that latch might, more properly, be considered as path of the external logic the custom interface in connected to.