Critical Warning

There is no syntax problem with your VHDL/Verilog code. You just need to constrain your clocks/IO to get rid of your unconstrained paths. At the very least, constrain your clocks. Trust me, this is a must.

For most designs, one must create an .SDC file. This file will contain information for Quartus on your clock speeds and the IO requirements. (which clock each pin on your fpga is referenced to)

If you run the timequest timing analyzer (with your project open), on the left side there should be a "report unconstrained paths" (in the "Tasks" on the left, you will need to scroll down just a bit) Double click on it and in the Quartus report window there will be a new set of information on the left. It will tell you what I/O in your design is not fully constrained.

If you go to File->New... create a Synopsis Design Constraints (SDC) file. This will begin your process to constrain your design. I recommend that if you have not already opened the timequest timing analyzer and reported your unconstrained paths, do it now. (once it is done, leave that window open - if you close it, the .SDC editor in Quartus won't help you create your constraints)

The first thing I constrain is my clock. Afterwards I constrain my I/Os. Some paths are not really critical (i.e. LEDs). These are set as "false paths" in the .SDC file (letting timequest know it can ignore the path).

I hope this helps and isn't too much info.