Critical path of a circuit , modelsim

Hello Tricky,

I am doing RTL simulation of a memory module. It is a synchronous design.

The design has an address comparator (which is a combinational circuit) connected to a memory. The simulation wave forms indicate that when there is an address conflict the memory takes 2 clock cycle for a write operation. Otherwise it just takes one cycle. I was trying to figure out where the extra clock delay is coming from since there are no registers adding that delay.