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Did you try giving constraints in SDC and compiling the design?
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Actually, I'm trying to explore constraints for a particular DU design and how multi stage pipeline affects the clocking scheme. For experimental purpose, I wanted to implement the design on FPGA and test the DU design with various case study. It is easier to use FPGA because it is reprogrammable. Before designing the DU, I need to get all information about this.
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I assume you realize that the "logic gate" in the FPGA is implemented in a LUT. The delays are device family, speed grade, and timing model dependent. I don't think you will find these values in a data sheet if that's what you are looking for. The best way to determine the delay is to use the report_timing command (if the path is constrained) or report_path command (if it is not constrained) in TimeQuest, and then look at the path details. TimeQuest will report the IC (interconnect) and CELL ("logic gate") delays there for the path in question.
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Now that I know that the "logic gate" is implemented in a LUT and the delay depends on device familiy. I guess I have to depend on TimeQuest to get the critical path delay and estimate the clocking speed.
Thank you for replying :D
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