Critical Path Delay Calculation: Component Delay information

I assume you realize that the "logic gate" in the FPGA is implemented in a LUT. The delays are device family, speed grade, and timing model dependent. I don't think you will find these values in a data sheet if that's what you are looking for. The best way to determine the delay is to use the report_timing command (if the path is constrained) or report_path command (if it is not constrained) in TimeQuest, and then look at the path details. TimeQuest will report the IC (interconnect) and CELL ("logic gate") delays there for the path in question.