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I would like the simulation process to be as simple as possible at the moment. I feel that even though a test bench will probably be the better solution later in the project, i feel that it has a steeper learning curve to be able to get up to the stage where i can comfortably simulate a project without spending a considerable amount of time on it.
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You cannot avoid the learning curve. The Modelsim wave editor produces a VHDL or Verilog file that you then need to connect to your logic. So the only step you are 'changing' by using the waveform editor is that you are manually creating the waveforms using a graphical editor, rather than typing in VHDL.
I can understand that using Qsim looks to be easier. However, spend a few minutes and run the modelsim_example.zip example and you'll see that its not really that much effort.
Cheers,
Dave
Honored Contributor
