create_generated_clock latency

Hello Altera,

The below link

http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html]

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Source latencies are based on clock network delays from the master clock (not necessarily the master pin). You can use the set_clock_latency -source command to override the source latency.

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Can someone help me to understand how latency is calculated exactly in Quartus for create_generated_clock.

Regards,

frk