CRC issues with Stratix II

I haven't worked with the megafunction directly, but have done a CRC on my own. It had to match the simulation of another CRC generator, and was one of the worst projects I've worked on, as far as not approaching it correctly. The largest problem is that what you get out is either correct, or completely wrong, with nothing in between to give you an idea of what's working and what isn't. So if I had an error in my XOR tree(which I did), all the byte flipping, byte swapping(I was feeding 2 bytes at a time), inverting, power-up changing became a distraction. In your case, I assume it is correct, but I would add some basic control signals to manually flip the byte order and/or invert it coming in. On the output side I would bring out all four possibilities(untouched, flipped, inverted, flipped and inverted). Then run the same packet through multiple times in a simulation, and with your control signals trying every combination of going in. (I've seen a couple CRCs and, including mine, they all powered up to 1, so start with that, but if none of this works, try the inverse.) I know this sounds like a really dumb way to do it, but if you'll spend/waste a lot more time trying to figure out how the CRC works or intelligently figure out "what is wrong", when you're just trying to get it to work.