Hi, I have got questions regarding the CRC capability of Cyclone V devices: The following document describes the behaviour on pages 291 - 301: https://www.intel.com/content/dam/www/programmable/us...
--> I think, you mean "Setting cannot be change as the oscillator is fixed.", right?
Yes, you are correct.
There is error on the calculation of the minimum time where the bracket should be there.
--> So, I assume, the right formula is as shown above, can you confirm?
Yes, I already feedback this issue to be fixed in next released.
The Table 106 is showing the time for full device CRC calculation.
--> What do you mean with "Table 106"? I guess, you are talking about "Table 8-3: Device EDCRC Detection Time in Cyclone V Devices". Can you confirm?
--> So, I understand, that this table already shows the minimum and maximum detection time for CRC errors in the whole device and I don't have to calculate those numbers. Did I get this right?
Yes. but if you need specific divider used in your design then you can calculate what is the maximum and minimum time needed.
So the Tmax is calcluated based on the maximum divisor factor of n = 8. So 13.93s = 2^(8-8)*13.93s.
--> Ok.
The Tmin is calculated based on the minimum divisor factor based on the device minimum divisor setting supported. For Cyclone V E A9 then it will be 23s = 2^0 / 1 * 23. The value Divisor Setting is 2 ^ n. So n = 0 when the divisor setting is 1 ( 2^0 = 1).
--> The result is 23ms and not 23s, right? I have to be very sure, that I get this right...