CRC Compiler Inconsistent Results

I am using the CRC compiler to create a CRC32 Ethernet Frame Checksum (FCS) [Quartus 12.0, lastest sp -- 1 channel, 32 bits, 4 symbols/word, CRC-32, optimized for speed, all 1's starting, 0 offset, negated checksum, registers on both input/output]

I created the module and a quick Modelsim test bench. I am getting odd results.

the test

I generated an Ethernet frame using Ostinato and captured it on the TSE on my board, just to make sure that I have an accurate FCS. I use this frame as test data in Modelsim. I'm using the .VHO model rather than the fully compiled code (although I will try that soon).

I can't get the CRC result to match up with the captured frame. I'm pretty sure that I have the correct byte ordering, but, just in case, I tried re-ordering the bytes. No luck.

state seems to be kept between frames

However, what is very disturbing is that if I create a loop around my packet dump code and send the same Avalon packet data several times, the CRC32 generator gets different results; some state seems to be kept between frames. This is just wrong. I've used the Avalon streaming fabric in a few previous designs so I'm pretty sure that I'm not doing something completely boneheaded (famous last words, eh?). The waveforms match up with the core manual.

Has anyone had experience with the CRC core, good or bad?