Forum Discussion
Rahul_S_Intel1
Frequent Contributor
7 years agoHi ,
This is the feature provided in the Cyclone 10 LP.There is a hard block (circuitry ) for the error detection cyclic redundancy check (CRC). To enable you can use 7.4 section of the below document.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf
Regards,
Rs
MFerr15
New Contributor
7 years agoHi, thank for your reply. As I mentioned in my post above I read the handbook, but there isn't any mention to a formula to calculate these times. In other handbook (e.g. Cyclone V) there are formulas describing the maximum and minimum times for the different frequency dividers (in page 288 of the Cyclone V handbook 1). Should I assume the formula is the same? If not how do I calculate.
I also don't find any answers to my other questions in the handbook, namely the speed grades of the devices..
Cheers