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Altera_Forum's avatar
Altera_Forum
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12 years ago

CPLD vs FPGA:

So Lets say I wish to analyse pixel streams ( uncompressed DVI) I HAVE A 1 SECOND/16 000 000 time time window, until the next pixel. Multiple 24 bit parallel RGB combinations activate cert...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The flex 6000 series is very old (about 15-20 years!) so you may struggle to find parts.

150ns is only 15 clocks at 100 Mhz (but your pixel clock will be slower than this). With different clocks, you'll need fifos to get across the clock domains, which is usually easier with a line buffer.

Why cant you just buffer the video in the FPGA and then forward it out of the FPGA?