Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCPLD vs FPGA:
So Lets say I wish to analyse pixel streams ( uncompressed DVI) I HAVE A 1 SECOND/16 000 000 time time window, until the next pixel. Multiple 24 bit parallel RGB combinations activate cert...
Altera_ForumHonored Contributor
Honored Contributorso 150 ns is alot or little ??
No, no buffer, too much expense. Wouldnt be here if I ws gonna use buffer. I need something on 3.3 volt or 3.3v tolerant at least. Does altera make these or should I go lattice ?? What about the flex 6000 series, this too old ?? Those look 3.3 volt and pretty cheap. Cyclone 3 is so expensive @ 35$ on digikey.
