Forum Discussion
Altera_Forum
Honored Contributor
12 years agoCPLD vs FPGA:
So Lets say I wish to analyse pixel streams ( uncompressed DVI) I HAVE A 1 SECOND/16 000 000 time time window, until the next pixel. Multiple 24 bit parallel RGB combinations activate cert...
Altera_Forum
Honored Contributor
12 years agoThere will be no frame buffer, thats expensive...15$ per chip at least + a ram controller. I looked... big NO.
This MUST happen on the fly... AXH 175, what do you mean, is this timing reasonable or will the fpga actually be much faster than this ?? when the right color is there, 24 bit combination, turn on a pin. I must warn my ARM microcontroller, that does a simple task and gets ready for new pixel, wich could be the next one after. I need this on 3.3v also, if possible. or 3.3v tolerant I/O @ a minimum. Somebody plz provide me with a solution by altera.