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'Done' is just an input signal of the cpld,which is drivered by fpga.
that's all.
I haven't solve it yet.
thanks for your reply!
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That means 'Done' has a driver (as it is driven by an FPGA driver). Can you write about the following to make your query clearer:
1. Where are you observing 'Done' as '1': On an oscilloscope/logic analyzer or is it a simulation? If you are observing this on oscilloscope then clearly since the pin is driven by an FPGA, you are bound to see '1' or '0' or whatever it has been driven. If it is a simulation, and 'Done' is an input port then you will see only that value at 'Done' which you assign in your testbench.
2. You said Databus can be an "input/output". Do you mean it is an inout port? If yes then isn't it possible that it can be a source too rathen than just a sink?
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