CPLD clock skew generation

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My code decodes address,data,,cs and r/w from a processor bus. The data is written and read to a fifo based on fifo_read and fifo_write. Since the clock for the processor bus signals is the same as the fifo clock I just wanted a few ns delay between fifo_read/write (generated by a state machine) to make sure the fifo_clock is stable before the fifo_read/write happens.

Without any phase difference between the closks the current design seems to give unpredictable read/writes results.

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What you need to do is perform a timing analysis.

Quartus has a tool called TimeQuest. You need to create a timing constraints file that describes the processor bus timing to the TimeQuest tool. The fitter will then try to meet those timing requirements. If it does not meet the timing requirements, then it will indicate which paths are failing.

The Altera wiki has a nice guide written by Rysc:

http://www.alterawiki.com/wiki/timequest

Cheers,

Dave