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Honored Contributor
Honored ContributorCPLD acting strangely
Hello. I designed an interface between an FPGA and a CPLD (MAXII) which is not entirely synchronous. The interface consists of 3 lines: Data, Clock and Enable. Each command transfered is 32 bits l...
Altera_ForumHonored Contributor
Honored ContributorSince there are very little inputs, I was able to see with a scope that they are exactly those that I simulated in the timing simulation (so I can guess that we can rule out wrong inputs to the simulation). In addition, the design was suppoused to work at 20MHz, and we reduced the working frequency to about 1MHz, still to have this problem. I guess that the timing simulation might not be simulating correctly what happens in the internal logic (as you suggested).
Is there a way to make a more accurate simulation than the timing simulation in Quartus? If not, is it possible to find the bug by looking at the RTL or something of that sort?
