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As far as I know the Altera remote update IP core is a softcore, not hardcore; i.e. It can exist in the FPGA using some logic cells or it may not exist at all if you do not want remote update feature.
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I guess I was mislead by the terminology then, Cyclone V's handbook volume 1 says the following: "Cyclone V devices contain dedicated remote system upgrade circuitry." in page 7-35, it sounds as it would be dedicated hardware rather than soft logic. I understand the remote_update IP is indeed soft logic, however, the underlying hardware would seem to be hardcore, right?
What I'm trying to figure out is how reliable the WatchDog is, in case a SEU causes my device to stop working correctly I need to be certain a reconfiguration will be triggered.
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One you enable the CRC option, that pin will be used for CRC feature. It cannot be used for any other purposes. It is available to you for error detection mechanisms & you can use it for error detection.
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In my case I only need the CRC check to trigger a reconfiguration (which is then reported by the status register in the remote_update IP), is this the only way to enable that?
I'm on the same boat as with the watchdog here, I need to make certain that if, for whatever reason, the FPGA's configuration becomes corrupted a reconfiguration is triggered. Unfortunately, I don't have an external device who can monitor the CRC pin so I need to do it all internally, it would be nice if I didn't have to dedicate a pin for that (given that it'd become basically useless in such case) but if that's the only option then that's fine, I'll accommodate for it.
Thank you for your help!
Regards,
Sebastian.
Honored Contributor
